1. Field of the Invention
This invention relates to a method for fabricating a semiconductor device, and more particularly to a method for forming a multi-level interconnection in a semiconductor device.
2. Description of the Related Art
When a fine pattern is formed as high integration of semiconductor devices, assurance of overlap margin due to reduction of linewidth is demanded. FIG. 1A to FIG. 1F show sectional views illustrating a method for forming a multi-level metal interconnection. Referring to FIG. 1A, an insulating layer 13 is formed over an underlying layer 191 including a first metal interconnection 12 such as a substrate or as an insulating layer. The insulating layer 13 is etched to form contact hole 13xe2x80x2 where a contact plug is to be formed, thereby exposing the first metal interconnection 12. Referring to FIG. 1B, a metal film for metal plug 14 is deposited so as to be filled in the contact hole 13xe2x80x2 and the metal film 14 is etched with a chemical mechanical polishing (CMP) method to form a metal plug 14xe2x80x2 as shown in FIG. 1C.
As shown in FIG. 1D, a metal film for second metal interconnection 15 having high conductivity such as Al is deposited over the underlying layer 11 and as shown in FIG. 1E, a photosensitive film 16 is coated on the metal film for second metal interconnection 15 and then patterned. As shown in FIG. 1F, using the patterned photosensitive film 16 as a mask, the metal film 15 is etched to form a second metal interconnection 17.
However, the prior method using the metal plug has a draw back as follows. After etching the metal film for second metal interconnection, a tip is formed in the metal stringer within the contact hole, thereby degrading the device property and acting as the defect factor to reduce yield. Furthermore, the pattern overlap margin between the second metal interconnection formed over the insulating layer and the first metal interconnection formed below the insulating layer is reduced and the production yield and property are degraded with reduction of process margin, as the pattern size is diminished more and more.
FIG. 2A to FIG. 2D show sectional views illustrating a method for forming a multi-level metal interconnection. A first metal interconnection 22 is formed on an underlying layer 21 such as a substrate or an insulating layer as shown in FIG. 2A and an insulation process for metal interconnection is carried out as shown in FIG. 2B. That is, a first insulating layer 23 having good step coverage and insulation properties is formed the underlying layer 21 including the first metal interconnection 22. A second insulating layer 24 for planarization is formed on the first insulating layer 23 and finally a third insulating layer 25 is formed on the second insulating layer 24.
As shown in FIG. 2C, a photosensitive film 26 is formed on the third insulating layer 25. As shown in FIG. 2D, the first to third insulating layers 23-25 are etched using the photoresist film 26 as a mask to form a contact hole, thereby exposing the first metal interconnection 22. A second metal interconnection 27 is formed on the third insulating layer 25 to contact with the first metal interconnection 22 through the contact hole.
The prior method has drawbacks as follows. As high integration of semiconductor memory devices, a line and a space of the metal interconnection are smaller so that a void is generated in forming the insulation layer for metal interconnection as shown in FIG. 3A. The void brings about lifting phenomenon of the insulating layer in the following heat treatment so that the critical damage of the device is occurred.
Besides, if misalignment is occurred in the photoetching process for forming the contact hole, when the second metal interconnection is formed following the contact hole formation process using the photosensitive, the overlap margin becomes smaller as shown in FIG. 3B. Accordingly, the electrical property of the device is degraded and mass production is very difficult with lack of the photoetching process margin.
It is an object of the present invention to provide a method for forming a multi-level metal interconnection of a semiconductor device with a metal plug, capable of improving the overlap margin between patterns and metal interconnection property using a metal spacer.
It is another object of the present invention to provide a method for forming a multi-level metal interconnection of a semiconductor device, capable of improving the planarization degree of the metal intermediate insulating layer, preventing occurrence of a void and assuring the sufficient process margin using a metal spacer.
According to an aspect of the present invention, there is provided to a method for forming a multi-level metal interconnection of a semiconductor device, comprising the steps of: forming a first metal interconnection on an underlying layer; forming an insulating layer over the underlying layer including the first metal interconnection; etching the insulating layer to form a contact hole, thereby exposing the first metal interconnection; forming a metal plug in the contact hole; further etching the insulating layer by a thickness; forming metal spacers in sidewalls of the metal plug over the insulating layer; and forming a second metal interconnection over the insulating layer to contact with the first metal interconnection through the metal spacer.
In the formation step of the metal plug, a tungsten plug is deposited over the insulating layer including the contact hole and then etched with a CMP process to form the metal plug. In the etching step of the insulating layer, the insulating layer is etched using an oxide target to have a height lower than the metal plug. Following the formation step of the second metal interconnection, the method of this invention further includes the step of removing the metal spacer which is not contacted with the metal plug.
There is also provided to a method for forming a multi-level metal interconnection of a semiconductor device, comprising the steps of: forming a first metal interconnection on an underlying layer; forming a first insulating layer over the underlying layer including the first metal interconnection; etching the first insulating layer to have a height lower than the first metal interconnection, thereby forming a height difference; forming metal spacers in sidewalls of the first metal interconnection over the first insulating layer; forming a planarization film over the whole surface of the underlying layer including the metal spacers; etching the planarization film to form a contact hole, thereby exposing the first metal interconnection; and forming a second metal interconnection over the planarization film to contact with the first metal interconnection through the contact hole.
The first insulating layer is etched by a wet or dry etching process. In etching the first insulating layer, a freon gas or a diluted gas of CO, O2, Ar and He is used to increase the etching selectivity to the first metal interconnection.
The planarization film formation step includes the step of forming a second insulating layer having good planarization property over the underlying layer and the step of forming a third insulating layer over the second insulating layer.